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| 1CY 54/7 4FCT543 T fax id: 7040 CY54/74FCT543T 8-Bit Latched Registered Transceiver Features * Function, pinout, and drive compatible with FCT and F logic * FCT-C speed at 5.3 ns max. (Com'l) FCT-A speed at 6.5 ns max. (Com'l) * Reduced VOH (typically = 3.3V) versions of equivalent FCT functions * Edge-rate control circuitry for significantly improved noise characteristics * Power-off disable feature * Matched rise and fall times * Fully compatible with TTL input and output logic levels * ESD > 2000V * Sink current 64 mA (Com'l), 48 mA (Mil) Source current 32 mA (Com'l), 12 mA (Mil) * Separation controls for data flow in each direction * Back to back latches for storage * Extended commercial range of -40C to +85C Functional Description The FCT543T octal latched transceiver contains two sets of eight D-type latches with separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input must be LOW in order to enter data from A or to take data from B, as indicated in the truth table. With CEAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their output no longer change with the A inputs. With CEAB and OEAB both LOW, the three-stage B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Functional Block Diagram Detail A DQ LE A0 QD LE B0 Logic Block Diagram A0 CEAB CEBA LEAB LEBA A1 A2 A3 A4 A5 A6 A7 OEBA OEAB CEBA CEAB LEBA LEAB B1 B2 B3 B0 A1 A2 A3 A4 A5 A6 A7 OEAB OEBA B1 B2 B3 B4 B5 B6 B7 Detail A x 7 B4 B5 B6 B7 Pin Configurations SOIC/QSOP Top View LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 May 1994 - Revised March 17, 1997 CY54/74FCT543T Pin Description Name OEAB OEBA CEAB CEBA LEAB LEBA A B Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A Three-State Outputs B-to-A Data Inputs or A-to-B Three-State Outputs Maximum Ratings[4, 5] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -65C to +135C Supply Voltage to Ground Potential ...............-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V DC Output Voltage .........................................-0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation.......................................................... 0.5W Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch OEAB X X H L L A-to-B[3] Storing Storing X Transparent Storing Outputs B High Z X High Z Current A Inputs Previous A Inputs Function Table[1, 2] Inputs CEAB H X X L L LEAB X H X L H Operating Range Range Commercial Commercial Military[6] Range DT T, AT, CT All Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 5% 5V 5% 5V 10% Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. 2. A-to-B data flow shown: B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. 3. Before LEAB LOW-to-HIGH Transition. 4. Unless otherwise noted, these limits are over the operating free-air temperature range. 5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 6. TA is the "instant on" case temperature. 2 CY54/74FCT543T Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions VCC=Min., IOH=-32 mA VCC=Min., IOH=-15 mA VCC=Min., IOH=-12 mA VOL VIH VIL VH VIK IIH IIH IIL IOZH IOZL IOS IOFF Output LOW Voltage Input HIGH Voltage Input LOW Voltage Hysteresis[8] Input Clamp Diode Voltage Input HIGH Current Input HIGH Current[8] Input LOW Current[8] Off State HIGH-Level Output Current Off State LOW-Level Output Current Output Short Circuit Current[9] Power-Off Disable All inputs VCC=Min., IIN=-18 mA VCC=Max., VIN=VCC VCC=Max., VIN=2.7V VCC=Max., VIN=0.5V VCC=Max., VOUT = 2.7V VCC= Max., VOUT = 0.5V VCC=Max., VOUT=0.0V VCC=0V, VOUT=4.5V -60 -120 0.2 -0.7 -1.2 5 1 1 10 -10 -225 1 VCC=Min., IOL=64 mA VCC=Min., IOL=48mA Com'l Com'l Mil Com'l Mil 2.0 0.8 Min. 2.0 2.4 2.4 3.3 3.3 0.3 0.3 0.55 0.55 Typ.[7] Max. Unit V V V V V V V V V A A A A A mA A Capacitance[8] Parameter CIN COUT Input Capacitance Output Capacitance Description Typ.[7] 5 9 Max. 10 12 Unit pF pF Notes: 7. Typical values are at V CC=5.0V, TA=+25C ambient. 8. This parameter is guaranteed but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY54/74FCT543T Power Supply Characteristics Parameter ICC ICC ICCD Description Test Conditions Typ.[7] 0.1 0.5 0.06 Max. 0.2 2.0 0.12 Unit mA mA mA/MHz Quiescent Power Supply Current VCC=Max., VIN0.2V, VINVCC-0.2V Quiescent Power Supply Current VCC=Max., VIN=3.4V,[10] (TTL inputs) f1=0, Outputs Open Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, CEAB and OEAB=LOW, CEBA=HIGH, VIN0.2V or VINVCC-0.2V Total Power Supply Current[12] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW,CEBA=HIGH, f0=LEAB = 10 MHz, VIN0.2V or VINVCC-0.2V VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN=3.4V or VIN=GND VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN0.2V or VINVCC-0.2V VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN=3.4V or VIN=GND Notes: 10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+ICCDHNT +ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. IC 0.7 1.4 mA 1.2 3.4 mA 2.8 5.6[13] mA 5.1 14.6[13] mA 4 CY54/74FCT543T Switching Characteristics Over the Operating Range[14] FCT543T Military Parameter tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tS tH tW Description Propagation Delay Transparent Mode A to B or B to A Propagation Delay LEBA to A, LEAB to B Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B Set-Up Time HIGH or LOW, A or B to LEBA or LEAB Hold Time HIGH or LOW, A or B to LEBA or LEAB Pulse Width LOW[8] LEBA or LEAB Min.[14] 2.0 2.5 2.0 Max. 10.0 14.0 14.0 Commercial Min.[14] 2.5 2.5 2.0 Max. 8.5 12.5 12.0 FCT543AT Commercial Min.[14] 2.5 2.5 2.0 Max. 6.5 8.0 9.0 Unit ns ns ns Fig. No.[15] 1, 3 1, 5 1, 7, 8 2.0 13.0 2.0 9.0 2.0 7.5 ns 1, 7, 8 3.0 2.0 5.0 2.0 2.0 5.0 2.0 2.0 5.0 ns ns ns 9 9 5 FCT543CT Commercial Parameter tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tS tH tW Description Propagation Delay Transparent Mode A to B or B to A Propagation Delay LEBA to A, LEAB to B Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B Set-Up Time, HIGH or LOW, A or B to LEBA or LEAB Hold Time, HIGH or LOW, A or B to LEBA or LEAB Pulse Width LOW LEBA or LEAB[8] Min.[14] 2.5 2.5 2.0 Max. 5.3 7.0 8.0 FCT543DT Commercial Min.[14] 1.5 1.5 1.5 Max. 4.4 5.0 5.4 Unit ns ns ns Fig. No.[15] 1, 3 1, 5 1, 7, 8 2.0 6.5 1.5 4.3 ns 1, 7, 8 2.0 2.0 5.0 1.5 1.5 3.0 ns ns ns 9 9 5 Shaded areas contain preliminary information. Notes: 14. Minimum limits are guaranteed but not tested on Propagation Delays. 15. See "Parameter Measurement Information" in the General Information Section. 5 CY54/74FCT543T Ordering Information Speed (ns) 4.4 5.3 6.5 8.5 10.0 Ordering Code CY74FCT543DTSOC CY74FCT543DTQC CY74FCT543CTQC CY74FCT543CTSOC CY74FCT543ATQC CY74FCT543ATSOC CY74FCT543TQC CY74FCT543TSOC CY54FCT543TDMB Package Name S13 Q13 Q13 S13 Q13 S13 Q13 S13 D14 Package Type 24-Lead (300-Mil) Molded SOIC 24-Lead (150-Mil) QSOP 24-Lead (150-Mil) QSOP 24-Lead (300-Mil) Molded SOIC 24-Lead (150-Mil) QSOP 24-Lead (300-Mil) Molded SOIC 24-Lead (150-Mil) QSOP 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP Document #: 38-00264-B Military Commercial Commercial Commercial Operating Range Commercial Shaded areas contain preliminary information. 6 CY54/74FCT543T Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D-9 Config.A 24-Lead Quarter Size Outline Q13 7 CY54/74FCT543T Package Diagrams (continued) 24-Lead (300-Mil) Molded SOIC S13 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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